This invention relates generally to the field of communication of digital information, and more particularly to a computing system having adaptive communication components for eliminating process-dependent and data-dependent communication errors.
Error-free communication between components of a computing system is critical for accurate computing. Communication error may be caused by many factors. First, transmittal rates between components in similar computing systems are greatly affected by variations in the fabrication process for the individual components. For this reason, computing systems are often designed assuming a worst-case transmittal rate even though the actual achievable rate may be much faster. Second, the effects of such process-dependent errors are often a function of the data being communicated. This is particularly true in systems having source-terminated transmission lines. These systems are often susceptible to jitter where the actual transmittal rate varies with transmitted data.
Error-free communication becomes even more difficult as the clock speeds for modem computing systems continually increase. Conventional communication designs often incorporate a data queue, such as a FIFO, to store and transmit data between components. This technique introduces severe latencies which are unacceptable for data communication within modem computing systems. As a result, many computing systems have implemented custom communications designs in an attempt to minimize communication latency. These custom designs, however, often need to be continually redesigned as clock speeds increase. Furthermore, various components of a computing system often communicate at different rates. For example, multiple processors on a single printed circuit board may communicate at over 300 MHZ while communications with memory or another component over a back panel is often at a lower rate such as 100 MHZ. Custom communication designs have difficulty handling the varying communication rates of a modem computing system and often need to be redesigned for each communication stream.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a computing system which reduces process-dependent communication error and data-dependent communication error. There is also a need for a computing system that is adaptive and can easily be used in a variety of computing systems at a variety of communication rates.
The present invention is directed toward an adaptive computing system for reducing harmful skew caused by lengthy transmission lines. As illustrated in detail below, the system reduces data-dependent communication jitter and errors caused by process-dependent variations. In one embodiment, the invention is a data receiver including an input port having a plurality of data latches. Each data latch receives data from a transmission line and stores the data according to a unique clock signal. A data selector coupled to the input port selects one of the data latches and provides the stored data of the selected data latch to an output port. According to one feature, the data receiver comprises a test interface for commanding the data selector to select the data latch as a function of stored configuration information. According to another feature, the test interface stores the configuration information as a plurality of bits, each bit corresponding to one of the data latches and indicating whether the respective data latch stores accurate data. According to yet another feature, the test interface is a boundary scan register that accepts standard JTAG instructions for testing the receiver and user-defined instructions for programming the configuration information.
In another embodiment, the present invention is a data transmitter that includes an output latch for providing a data value to a transmission line. A precompensation control of the data transmitter provides a precompensation signal to the output latch when a change in the data value is detected. The output latch precompensates the transmission line according to the precompensation signal. According to one feature, the transmitter includes a test interface that is coupled to the precompensation control. The test interface enables and disables precompensation according to a configured precompensation mode. According to yet another feature, the test interface includes a boundary scan register that accepts standard JTAG instructions for testing the transmitter and user-defined instructions for configuring the precompensation mode.
In yet another embodiment, the present invention is a computing system having a transmitter coupled to a receiver by a transmission line. The transmitter provides a data value to the transmission line according to an output clock signal and precompensates the transmission line when a change in the data value is detected. The receiver has a plurality of data latches, each data latch storing a data value received from the transmission line according to a unique clock signal.
In another embodiment, the present invention is a method for communicating data in a computing system having a transmitter communicatively coupled to a receiver by a transmission line. The method includes the steps of transmitting data to the receiver via the transmission line and storing data received from the transmission line in a plurality of data latches according to a plurality of clock signals. According to one feature, the method includes the step of precompensating the transmission line when a change in the data value is detected. According to another feature, the method includes the step of selecting one of the data latches as a function of configuration information maintained in the receiver.
These and other features and advantages of the invention will become apparent from the following description of the preferred embodiments of the invention.